/*
 * Copyright 2024 ywcai
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

`include "../core/defines.v"
`timescale 1ns/1ps

module myriscv_tb(
	);
	reg				CLOCK_50;
	reg				rst_n;
	reg[`IrqBus]	irq;
//	integer			fd_inst;
//	integer			err;
//	integer			fd_ram;

	initial begin
		CLOCK_50 = 1'b0;
		forever #10 CLOCK_50 = ~CLOCK_50;
	end

	initial begin
		rst_n = `RESET_ENABLE;
		irq = 8'h0;
		#195 rst_n = `RESET_DISABLE;

//	for load test cases
//		fd_ram = $fopen("my.ds", "rb");
//		err = $fread(i_riscv_top.i_ram._ram, fd_ram);
//		$fclose(fd_ram);

		#1000000 $stop;
	end

    initial begin
        $readmemh("myriscv.bin", i_riscv_top.i_rom._rom);
//		fd_inst = $fopen("inst_rom.hex", "r");
//		err = $fread(i_riscv_top.i_rom._rom, fd_inst);
//		$fclose(fd_inst);
    end

	riscv_top i_riscv_top(
		.clk(CLOCK_50),
		.rst_n(rst_n),
		.irq_i(irq)
	);

endmodule
